The present invention relates to a flip flop device, a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit.
Gate array design and standard cell design are known procedures for designing semiconductor integrated circuit devices. In the gate array designing procedure, cells are arranged beforehand at predetermined positions and only wiring is performed. This procedure limits design freedom, but simplifies the design procedure.
In the standard cell designing procedure, circuits having certain functions and referred to as cells are prepared and arranged to form a circuit. As compared to the gate array design process, the standard cell design process achieves higher integration and increased functionality. Thus, the standard cell design process is used for designing a system on chip (SOC). In such a design process, a functional block diagram is first generated. Then, a detailed functional description is generated using a hardware description language. The detailed functional description undergoes functional testing with a functional simulator. For logic design, the functional block diagram and the detailed functional description are converted to specific hardware to generate a logic diagram (net list).
Next, layout is performed, where a circuit diagram is generated until a level enabling pattern of the logic expressed in the net list is generated. Then, a mask is generated to wire and connect devices of the circuit diagram on the semiconductor substrate.
In an actual LSI formed on a semiconductor substrate using the above process, circuits such as a flip flop that operates in accordance with a clock do not function normally unless setup and hold times are satisfactory. The setup time refers to the time during which a specified data signal is added and maintained before another input signal (clock signal) changes. The hold time refers to the time during which a specified data signal must be held after another input signal (clock signal) changes.
For example, in a logic LSI, wire delay is caused by wire resistance, wire capacitance, load capacitance, and the like. A delay is also produced when a signal passes through a logic gate. When a data delay or clock delay occurs due to such wire delay or logic gate delay, normal synchronous operations of flip flops are hindered. This may result in timing violations, such as setup time violations and data hold violations.
Therefore, in conventional circuit design processes, during logic design, wire delays that may actually occur are predicted after lay out. Then, timing analysis is performed based on the predicted wire delay, to determine where timing violations may occur so that changes may be made to the circuitry to satisfy the required timings.
Such an example will now be described with reference to FIG. 6. As shown in FIG. 6, a flip flop FF for use in a logic circuit includes two latch circuits (L1 and L2). A clock signal CK is used to generate an output signal Q from a data signal D.
In a circuit including two or more flip flops, with a clock tree synthesis (CTS) of a common clock source, a clock signal is synchronously provided to each flip flop FF from a clock generation circuit.
However, when cross talk noise enters a clock signal line, the clock signal provided to a flip flop FF in a latter stage may be delayed. In such a case, the output signal Q of a flip flop FF in a former stage is provided to a flip flop FF in a latter stage before the clock signal. This may cause a hold time violation.
Japanese Laid-Open Patent Publication No. 8-77227 (FIG. 1) discloses a technique for avoiding such a timing violation. In this technique, when designing the layout of an integrated circuit such as a gate array or a standard cell, devices are laid out so that deficiencies related with cross skew or hold time do not occur. More specifically, the number of gate circuits inserted in data signal paths between flip flops is counted. Flip flops for paths having a relatively large number of gate circuits are laid out near one another. Flip flops for paths having a relatively small number of gate circuits are laid out distant from one another.
To eliminate hold time violations, as shown in FIG. 7, the output terminal of a flip flop FF in a former stage is connected to the input terminal of a flip flop FF in a latter stage via plural stages of buffers B in accordance with a delay. This enables adjustment of the timing of the clock signal CK and the data signal D provided to the subsequent stage flip flop FF.
Japanese Laid-Open Patent Publication No. 2001-44287 (FIG. 1) discusses a method for designing a semiconductor integrated circuit that prevents hold time violations while enabling higher integration. In the technique described in this publication, when logic synthesizing is performed, restrictions are not applied for hold time violations but are applied for setup time violations. Timing analysis of a net list is performed. When a hold time violation is located in a path between flip flops FF, the flip flops FF are replaced by a correction flip flop FF unit. The correction flip flop FF unit includes delay circuits connected in front of a data input terminal and behind a data output terminal. Further, the correction flip flop FF unit is registered in a library in a unitized state with a minimized cell area.
The delay time differs depending on the circuit layout or the like. Thus, delay circuits (buffers) may not be able to avoid hold time violations. Further, the insertion of delay circuits depending on the circumstances makes circuit designing difficult. The insertion of such buffers or inverters increases the cell area and causes the wiring to be dense. In such a case, designing may physically become impossible.
Particularly, in a deep submicron process of 130 nm or less, setup time violations may be eliminated. However, the finer wires may increase the hold time violations. In the deep submicron process, the propagation delay of a clock signal due to cross talk noise or a decrease in the power supply voltage becomes prominent. Such clock fluctuation worsens skew and causes serious hold time violations. Further, since the hold time is not dependent on frequency, the problem of hold time violations cannot be solved by lowering the frequency. Thus, there is a possibility that abnormal functioning will occur.